Regviz

Espressif Systems /ESP32-S3 /EXTMEM /DCACHE_PRELOAD_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DCACHE_PRELOAD_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/EXTMEM/DCACHE_PRELOAD_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DCACHE_PRELOAD_ENA)DCACHE_PRELOAD_ENA 0 (DCACHE_PRELOAD_DONE)DCACHE_PRELOAD_DONE 0 (DCACHE_PRELOAD_ORDER)DCACHE_PRELOAD_ORDER

Description

******* Description ***********

Fields

DCACHE_PRELOAD_ENA

The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
DCACHE_PRELOAD_DONE

The bit is used to indicate preload operation is finished.
DCACHE_PRELOAD_ORDER

The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data